Functional test generation for full scan circuits

I Pomeranz; S.M Reddy

doi:10.1109/DATE.2000.840302

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Conference proceeding

Functional test generation for full scan circuits

I Pomeranz and S.M Reddy

Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537), pp.396-401

2000

DOI: 10.1109/DATE.2000.840302

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Abstract

We study the effectiveness of functional tests for full scan circuits. Functional tests are important for design validation, and they potentially have a high defect coverage independent of the circuit implementation. The functional fault model we consider consists of single state-transition faults. The test generation procedure we describe uses one of two approaches at any given time in order to minimize the number of tests while minimizing the test application time. (1) It may use scan to set the state of the circuit, and observe fault effects propagated to the next-state variables. (2) It may use transfer sequences to set the circuit state, or unique input-output sequences to propagate fault effects to the primary outputs. We present experimental results to demonstrate the effectiveness of scan-based functional tests.

Circuit faults

Circuit simulation

Circuit testing

Cities and towns

Delay

Electrical fault detection

Fault detection

Process design

Terminology

Details

Title: Subtitle: Functional test generation for full scan circuits
Creators: I Pomeranz - Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M Reddy
Resource Type: Conference proceeding
Publication Details: Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537), pp.396-401
Publisher: IEEE
DOI: 10.1109/DATE.2000.840302
ISSN: 1530-1591
eISSN: 1558-1101
Language: English
Date published: 2000
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197408902771

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