Conference proceeding
Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run
2018 IEEE International Test Conference (ITC), Vol.2018-, pp.1-10
10/2018
DOI: 10.1109/TEST.2018.8624678
Abstract
A novel test pattern generation flow for both DC and AC faults is presented. All faults to be processed are transformed into stuck-at faults with some constraints in a proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model which is supported by most commercial ATPG tools. This makes it possible to generate all required patterns for both DC and AC faults in one ATPG run with no need to modify the ATPG tool. A highly compact pattern set thus can be obtained which requires smaller test data volume and shorter test application time. The fault models considered in this paper include stuck-at faults, bridging faults and transition faults. Experiments on ISCAS'89, IWLS'05 and ITC'99 benchmark circuits show that, compared to the most efficient conventional methods, on average our method can reduce test pattern counts by 14.55%, 11.26% and 13.69% and reduce test application time by 25.93%, 24.47% and 31.67%, respectively, without degrading fault coverage.
Details
- Title: Subtitle
- Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run
- Creators
- Yi-Cheng Kung - National Cheng Kung UniversityKuen-Jong Lee - National Cheng Kung UniversitySudhakar M Reddy - University of Iowa
- Resource Type
- Conference proceeding
- Publication Details
- 2018 IEEE International Test Conference (ITC), Vol.2018-, pp.1-10
- Publisher
- IEEE
- DOI
- 10.1109/TEST.2018.8624678
- ISSN
- 1089-3539
- eISSN
- 2378-2250
- Language
- English
- Date published
- 10/2018
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197413002771
Metrics
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