Conference proceeding
Hyper-Graph Based Partitioning to Reduce DFT Cost for Pre-Bond 3D-IC Testing
2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE), pp.1424-1429
2011
DOI: 10.1109/DATE.2011.5763230
Abstract
3D IC technology has demonstrated significant performance and power gains over 2D. However, for technology to be viable yield should be increased. Testing a complete 3D IC after stacking leads to an exponential decay in yield. Pre-bond tests are required to insure correct functionality of the die. In this work we propose a hypergraph based biased netlist partitioning scheme scheme for pre-bond testing of individual dies to reduce extra-hardware (flip-flops) required. Further reduction in hardware is achieved by a logic cone based flip-flop sharing scheme. Simulation results on ISCAS89 benchmark circuits and several industrial benchmarks demonstrate the effectiveness of the proposed approach.
Details
- Title: Subtitle
- Hyper-Graph Based Partitioning to Reduce DFT Cost for Pre-Bond 3D-IC Testing
- Creators
- Amit KumarSudhakar M ReddyIrith PomeranzBernd Becker
- Resource Type
- Conference proceeding
- Publication Details
- 2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE), pp.1424-1429
- DOI
- 10.1109/DATE.2011.5763230
- Language
- English
- Date published
- 2011
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984232098702771
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