- Title: Subtitle
- ITEM:an iterative improvement test generation procedure for synchronous sequential circuits
- Creators
- Irith Pomeranz - Purdue University West LafayetteSudhakar M Reddy - University of Iowa
- Resource Type
- Conference proceeding
- Publication Details
- Great Lakes Symposium on VLSI: Proceedings of the 11th Great Lakes symposium on VLSI, pp.13-18
- Conference
- Great Lakes Symposium on VLSI, 11 (West Lafayette, IN, USA, 03/2001)
- DOI
- 10.1145/368122.368147
- Language
- English
- Date published
- 01/01/2001
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197905602771
Conference proceeding
ITEM:an iterative improvement test generation procedure for synchronous sequential circuits
Great Lakes Symposium on VLSI: Proceedings of the 11th Great Lakes symposium on VLSI, pp.13-18
Great Lakes Symposium on VLSI, 11 (West Lafayette, IN, USA, 03/2001)
01/01/2001
DOI: 10.1145/368122.368147
Details
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