Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration

Irith Pomeranz; Sudhakar M Reddy

doi:10.1109/VLSI.Design.2010.16

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Conference proceeding

Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration

Irith Pomeranz and Sudhakar M Reddy

2010 23rd International Conference on VLSI Design, pp.39-44

01/2010

DOI: 10.1109/VLSI.Design.2010.16

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Abstract

Bridging and interconnect open faults are defined using subsets of lines. We study the possibility of identifying input vectors that are effective as test vectors for such faults without enumerating the faults. This process does not require accurate layout information, it can handle very large numbers of faults, and it deals with undetectable faults implicitly. We describe a static test compaction process that uses the ability to identify effective test vectors without enumerating faults. This process selects a subset T of a given test set U such that T is guaranteed to detect the same faults as U. We also describe a test generation process based on the same concept. Finally, we show how this concept can be used to compare test sets.

Bridge circuits

bridging faults

Capacitance

Circuit faults

Circuit testing

Electrical fault detection

Fault detection

Fault diagnosis

Integrated circuit interconnections

interconnect open faults

Leakage current

Logic testing

static test compaction

test generation

Details

Title: Subtitle: Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration
Creators: Irith Pomeranz - Purdue University West Lafayette
Sudhakar M Reddy - University of Iowa
Resource Type: Conference proceeding
Publication Details: 2010 23rd International Conference on VLSI Design, pp.39-44
DOI: 10.1109/VLSI.Design.2010.16
ISSN: 1063-9667
eISSN: 2380-6923
Publisher: IEEE
Language: English
Date published: 01/2010
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197350802771

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