Conference proceeding
Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST
Proceedings of the 2002 Asia and South Pacific Design Automation Conference, pp.604-611
ASP-DAC '02
01/07/2002
DOI: 10.1109/ASPDAC.2002.995003
Abstract
New test point selection algorithms to improve test point insertion quality and performance of multi-phase test point insertion scheme, while reducing the memory requirement of the analyses are proposed. A new memory efficient probabilistic fault simulation method, which also handles the reconvergences to a limited extent for increased accuracy, is introduced. Synergistic control point insertion is targeted for higher test point insertion quality. Experiments conducted on various large industrial circuits demonstrate the effectiveness of the new algorithms.
Details
- Title: Subtitle
- Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST
- Creators
- Nadir BasturkmenSudhakar ReddyJanusz Rajski
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings of the 2002 Asia and South Pacific Design Automation Conference, pp.604-611
- Series
- ASP-DAC '02
- DOI
- 10.1109/ASPDAC.2002.995003
- Publisher
- IEEE Computer Society
- Language
- English
- Date published
- 01/07/2002
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197167402771
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