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Improving the proportion of at-speed tests in scan BIST
Conference proceeding

Improving the proportion of at-speed tests in scan BIST

Y Huang, I Pomeranz, S.M Reddy and J Rajski
IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140), Vol.2000-, pp.459-463
2000
DOI: 10.1109/ICCAD.2000.896514

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Abstract

Benchmark testing Built-in self-test Circuit faults Circuit testing Clocks Design optimization Frequency Power dissipation Sequential circuits System testing

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