Low Shift and Capture Power Scan Tests

Santiago Remersaro; Xijiang Lin; Sudhakar M Reddy; Irith Pomeranz; Janusz Rajski

doi:10.1109/VLSID.2007.101

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Conference proceeding

Low Shift and Capture Power Scan Tests

Santiago Remersaro, Xijiang Lin, Sudhakar M Reddy, Irith Pomeranz and Janusz Rajski

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), pp.793-798

01/2007

DOI: 10.1109/VLSID.2007.101

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Abstract

Supply current and power dissipation during scan based test may be much higher than during normal circuit operation due to larger switching activity caused by the tests. Higher peak current demands may cause supply voltage droops causing good chips to fail at-speed tests. Higher average switching activity causes higher power dissipation and chip temperature that may cause hot spots and damage circuits under test. Several works have proposed methods to derive tests with lower peak and average switching activity during test response capture or during scan shifts. Some of these methods require additional hardware and modifications to the scan chains. This paper investigates a method to derive tests with reduced switching activity both during scan shifts and during test response captures. The method does not require additional hardware or modifications to the scan chains. The proposed method accepts a given test set and returns a test set of the same or smaller size with reduced switching activity. Experimental results on benchmark and industrial circuits are given

Benchmark testing

Circuit faults

Circuit testing

Clocks

Current supplies

Delay

Hardware

Power dissipation

Switching circuits

Voltage

Details

Title: Subtitle: Low Shift and Capture Power Scan Tests
Creators: Santiago Remersaro - University of Iowa
Xijiang Lin - Mentor Graphics (United States)
Sudhakar M Reddy - University of Iowa
Irith Pomeranz - Purdue University West Lafayette
Janusz Rajski - Mentor Graphics (United States)
Resource Type: Conference proceeding
Publication Details: 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), pp.793-798
DOI: 10.1109/VLSID.2007.101
ISSN: 1063-9667
eISSN: 2380-6923
Publisher: IEEE
Language: English
Date published: 01/2007
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197165702771

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