Low capture power at-speed test in EDT environment

Elham K Moghaddam; Janusz Rajski; Sudhakar M Reddy; Xijiang Lin; Nilanjan Mukherjee; Mark Kassab

doi:10.1109/TEST.2010.5699275

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Conference proceeding

Low capture power at-speed test in EDT environment

Elham K Moghaddam, Janusz Rajski, Sudhakar M Reddy, Xijiang Lin, Nilanjan Mukherjee and Mark Kassab

2010 IEEE International Test Conference, pp.1-10

11/2010

DOI: 10.1109/TEST.2010.5699275

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Abstract

This paper presents a novel low capture power test scheme integrated with EDT (Embedded Deterministic Test) environment. The key contribution of this paper is to generate test vectors that in capture mode mimic functional operation from switching activity point of view. Experimental results presented for industrial circuits demonstrate the effectiveness of the proposed method.

Circuit faults

Clocks

Logic gates

Registers

Ring generators

Switches

Switching circuits

Details

Title: Subtitle: Low capture power at-speed test in EDT environment
Creators: Elham K Moghaddam - University of Iowa
Janusz Rajski - Mentor Graphics
Sudhakar M Reddy - University of Iowa
Xijiang Lin - Mentor Graphics
Nilanjan Mukherjee - Mentor Graphics
Mark Kassab - Mentor Graphics
Resource Type: Conference proceeding
Publication Details: 2010 IEEE International Test Conference, pp.1-10
DOI: 10.1109/TEST.2010.5699275
ISSN: 1089-3539
eISSN: 2378-2250
Publisher: IEEE
Language: English
Date published: 11/2010
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197186402771

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