Conference proceeding
MUSTC-testing: multi-stage-combinational test scheduling at the register-transfer level
The 8th International Conference on VLSI Design; New Delhi; India; 04-07 Jan. 1995, pp.110-115
International Conference on VLSI Design, 8 (New Delhi, India, 01/04/1995–01/07/1995)
01/04/1995
DOI: 10.1109/ICVD.1995.512087
Abstract
In this paper we discuss a new automatic test scheduling system for architectures that use separate control and datapaths. MULti - STage - Combinational Testing (MUSTC - Testing) at the Register-Transfer Level significantly eases test generation and can be used in lieu of or to complement sequential test generation at the gate level. We provide a system with eleven signal types to perform test scheduling at the RT level which allows module level pre-computed test sets to be directly used for testing. A test scheduler is then described along with the results obtained.
Details
- Title: Subtitle
- MUSTC-testing: multi-stage-combinational test scheduling at the register-transfer level
- Creators
- Sitaram YadavalliIrith PomeranzSudhakar M Reddy
- Resource Type
- Conference proceeding
- Publication Details
- The 8th International Conference on VLSI Design; New Delhi; India; 04-07 Jan. 1995, pp.110-115
- Conference
- International Conference on VLSI Design, 8 (New Delhi, India, 01/04/1995–01/07/1995)
- DOI
- 10.1109/ICVD.1995.512087
- ISSN
- 1063-9667
- Publisher
- IEEE
- Language
- English
- Date published
- 01/04/1995
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984198006702771
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