Conference proceeding
Minimal area test points for deterministic patterns
2016 IEEE International Test Conference (ITC), pp.1-7
11/2016
DOI: 10.1109/TEST.2016.7805825
Abstract
Conflict-aware test points, introduced recently, facilitate significant reductions in deterministic test pattern counts. However, dedicated flip-flops driving control points increase test logic area. This paper presents a method to minimize silicon area needed to implement conflict-aware test points by reusing functional flip-flops as drivers of control points. Conflict analysis is applied during the test point selection process, and ATPG verification is run for every potential candidate. Experimental results show that functional flip-flops can be reused as drivers for more than 90% of the control points with the average of 5% penalty in pattern count increase as compared to methods using only dedicated flip-flops. After replacing dedicated flip-flops with functional flip-flops, conflict-aware test points can still achieve remarkable pattern count reductions.
Details
- Title: Subtitle
- Minimal area test points for deterministic patterns
- Creators
- Yingdi Liu - University of IowaElham Moghaddam - Mentor GraphicsNilanjan Mukherjee - Mentor GraphicsSudhakar M Reddy - University of IowaJanusz Rajski - Mentor GraphicsJerzy Tyszer - Poznań University of Technology
- Resource Type
- Conference proceeding
- Publication Details
- 2016 IEEE International Test Conference (ITC), pp.1-7
- DOI
- 10.1109/TEST.2016.7805825
- ISSN
- 1089-3539
- eISSN
- 2378-2250
- Publisher
- IEEE
- Language
- English
- Date published
- 11/2016
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197286102771
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