NEST: A non-enumerative test generation method for path delay faults in combinational circuits

Irith Pomeranz; Sudhakar Reddy; Prasanti Uppaluri

doi:10.1145/157485.164967

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NEST: A non-enumerative test generation method for path delay faults in combinational circuits

Conference proceeding

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NEST: A non-enumerative test generation method for path delay faults in combinational circuits

Irith Pomeranz, Sudhakar Reddy and Prasanti Uppaluri

Proceedings of the 30th international Design Automation Conference, pp.439-445

DAC '93

Design Automation Conference, 30 (Dallas, Texas, 06/14/1993–06/18/1993)

07/01/1993

DOI: 10.1145/157485.164967

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Abstract

A test generation procedure for path delay faults is proposed, that targets all path delay faults in the circuit-under-test. The procedure overcomes the difficulties in handling the exorbitant numbers of path delay faults in practical circuits by using non-enumerative methods of considering faults, i.e., it never explicitly targets any specific path delay fault. Experimental results demonstrate the effectiveness of the method in deriving tests to detect very large numbers of path delay faults in short run times.

Details

Title: Subtitle: NEST: A non-enumerative test generation method for path delay faults in combinational circuits
Creators: Irith Pomeranz - University of Iowa
Sudhakar Reddy
Prasanti Uppaluri
Resource Type: Conference proceeding
Publication Details: Proceedings of the 30th international Design Automation Conference, pp.439-445
Conference: Design Automation Conference, 30 (Dallas, Texas, 06/14/1993–06/18/1993)
Series: DAC '93
DOI: 10.1145/157485.164967
ISSN: 0738-100X
eISSN: 2374-8818
Publisher: ACM
Language: English
Date published: 07/01/1993
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197919702771

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