Conference proceeding
On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic
Proceedings of the 2003 IEEE/ACM international conference on computer-aided design, pp.867-872
ICCAD '03
11/09/2003
DOI: 10.1109/ICCAD.2003.159777
Abstract
Design-for-testability (DFT ) for synchronous sequentialcircuits causes redundant faults in the original circuit to bedetectable in the circuit with DFT logic. It has beenargued that such faults should not be detected in order toavoid reducing the yield unnecessarily. One way to dealwith such faults is to mask (or ignore) their fault effectswhen they appear on the circuit outputs, without maskingthe detection of faults that need to be detected. To investigatethe extent to which this can be accomplished, wedescribe a procedure for masking the effects of redundantfaults of the original circuit under a given test set generatedfor the circuit with DFT logic. The procedureattempts to maximize the number of redundant faults thatare masked while minimizing (or holding to zero) thenumber of other masked faults.
Details
- Title: Subtitle
- On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic
- Creators
- Irith PomeranzSudhakar Reddy
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings of the 2003 IEEE/ACM international conference on computer-aided design, pp.867-872
- Publisher
- IEEE Computer Society
- Series
- ICCAD '03
- DOI
- 10.1109/ICCAD.2003.159777
- ISSN
- 1092-3152
- Language
- English
- Date published
- 11/09/2003
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197534902771
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