Conference proceeding
On RTL scan design
Proceedings International Test Conference 2001 (Cat. No.01CH37260), pp.728-737
2001
DOI: 10.1109/TEST.2001.966694
Abstract
This paper presents a methodology to insert scan paths in a functional Register Transfer Level (RTL) specification of a design that can exploit existing functional paths between sequential elements in the original circuit for establishing scan chains. The primary objective for RTL scan insertion is to reduce the time taken for DFT, and thus reduce the time to market. Additionally, building scan chains at the functional RT-Level is expected to reduce the total area overhead introduced by full scan without compromising the fault coverage achieved. In addition, it often eliminates the delay associated with the additional multiplexer as a part of a conventional scan-cell in high performance designs. Experimental results presented in this paper demonstrate that the proposed method achieves the above objectives while also achieving higher fault coverages for most of the benchmark circuits considered.
Details
- Title: Subtitle
- On RTL scan design
- Creators
- Yu Huang - University of IowaChien-Chung TsaiNilanjan Mukherjee - Mentor GraphicsOmer Samman - Mentor GraphicsDan Devries - Mentor GraphicsWu-Tung ChengSudhakar M Reddy - University of Iowa
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings International Test Conference 2001 (Cat. No.01CH37260), pp.728-737
- DOI
- 10.1109/TEST.2001.966694
- ISSN
- 1089-3539
- eISSN
- 2378-2250
- Publisher
- IEEE
- Language
- English
- Date published
- 2001
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197449402771
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