On Synthesis-for-Testability of Combinational Logic Circuits

Irith Pomeranz; Sudhakar Mannapuram Reddy

doi:10.1145/217474.217518

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Conference proceeding

On Synthesis-for-Testability of Combinational Logic Circuits

Irith Pomeranz and Sudhakar Mannapuram Reddy

32nd Design Automation Conference, pp.126-132

1995

DOI: 10.1145/217474.217518

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Abstract

We propose a synthesis method that modifies a given circuit to reduce the number of gates and the number of paths in the circuit. The synthesis procedure is based on replacing subcircuits of the given circuit by structures called comparison units. Comparison units are fully testable for stuck-at faults and for path delay faults. In addition, they have small numbers of paths and gates. These properties make them effective building blocks for synthesis of testable circuits. Experimental results demonstrate reductions in the number of gates and paths and increased path delay fault testability. The random pattern testability for stuck-at faults remains unchanged.

Circuit faults

Circuit synthesis

Circuit testing

Cities and towns

Combinational circuits

Delay

Electrical fault detection

Fault detection

Robustness

Timing

Details

Title: Subtitle: On Synthesis-for-Testability of Combinational Logic Circuits
Creators: Irith Pomeranz - University of Iowa
Sudhakar Mannapuram Reddy - University of Iowa, Electrical and Computer Engineering
Resource Type: Conference proceeding
Publication Details: 32nd Design Automation Conference, pp.126-132
DOI: 10.1145/217474.217518
ISSN: 0738-100X
Publisher: ACM
Language: English
Date published: 1995
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197450602771

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