On achieving complete coverage of delay faults in full scan circuits using locally available lines

I Pomeranz; S.M Reddy

doi:10.1109/TEST.1999.805824

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Conference proceeding

On achieving complete coverage of delay faults in full scan circuits using locally available lines

I Pomeranz and S.M Reddy

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), pp.923-931

International Test Conference (ITC) (Atlantic City, New Jersey, USA, 09/30/1999)

1999

DOI: 10.1109/TEST.1999.805824

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Abstract

We propose a testability enhancement technique for delay faults in standard scan circuits that does not involve modifications to the scan chain. Extra logic is placed on next-state variables, and if necessary, on primary inputs, and can be resynthesized with the circuit to minimize its hardware and performance overheads. The proposed technique allows us to achieve complete coverage of detectable delay faults. A simple test generation procedure that guarantees complete coverage when used with the proposed technique is also described.

Circuit faults

Circuit testing

Cities and towns

Design for testability

Electrical fault detection

Fault detection

Flip-flops

Logic circuits

Logic testing

Propagation delay

Details

Title: Subtitle: On achieving complete coverage of delay faults in full scan circuits using locally available lines
Creators: I Pomeranz - University of Iowa
S.M Reddy - University of Iowa
Resource Type: Conference proceeding
Publication Details: International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), pp.923-931
Conference: International Test Conference (ITC) (Atlantic City, New Jersey, USA, 09/30/1999)
Publisher: IEEE
DOI: 10.1109/TEST.1999.805824
ISSN: 1089-3539
eISSN: 2378-2250
Language: English
Date published: 1999
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984198004802771

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