Conference proceeding
On achieving complete testability of synchronous sequential circuits with synchronizing sequences
The 1994 IEEE International Test Conference; Washington, DC; USA; 02-06 Oct. 1994, pp.1007-1016
International Test Conference (ITC) (Washington, DC, USA, 10/02/1994–10/06/1994)
10/02/1994
DOI: 10.1109/TEST.1994.528050
Abstract
A completely testable circuit does not have any undetectable or redundant faults. We consider the problem of making synchronous sequential circuits that have synchronizing sequences completely testable for stuck-at faults. The method proposed is based on the removal of logic corresponding not only to redundant faults, but also to some undetectable yet irredundant faults. Thus, the proposed approach reduces the circuit size in addition to reducing or eliminating the extra hardware that may be otherwise necessary to render the circuit completely testable. A theoretical framework for achieving this goal was established earlier in [1]. In this work, we give a detailed procedure based on the concepts of [1] and give experimental results of its application.
Details
- Title: Subtitle
- On achieving complete testability of synchronous sequential circuits with synchronizing sequences
- Creators
- Irith PomeranzSudhakar M Reddy
- Resource Type
- Conference proceeding
- Publication Details
- The 1994 IEEE International Test Conference; Washington, DC; USA; 02-06 Oct. 1994, pp.1007-1016
- Conference
- International Test Conference (ITC) (Washington, DC, USA, 10/02/1994–10/06/1994)
- DOI
- 10.1109/TEST.1994.528050
- ISSN
- 1089-3539
- Language
- English
- Date published
- 10/02/1994
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197908302771
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