On avoiding undetectable faults during test generation

I Pomeranz; S.M Reddy

doi:10.1109/ETW.1999.804292

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Conference proceeding

On avoiding undetectable faults during test generation

I Pomeranz and S.M Reddy

European Test Workshop 1999 (Cat. No.PR00390), pp.90-95

1999

DOI: 10.1109/ETW.1999.804292

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Abstract

We use a property that distinguishes most of the undetectable faults in a circuit from detectable ones, in order to avoid targeting undetectable faults during test generation. We show that it is possible to avoid most of the undetectable faults until most of the detectable faults are detected. The test generation process is speeded-up by avoiding undetectable faults, since wasted effort expended in trying to detect undetectable faults is avoided. When all or most of the faults that remain undetected by the test generator appear to be undetectable faults, a procedure for identifying undetectable faults may be used. Detectable faults, if any such faults remain, may then be given to the test generator to obtain complete fault coverage. We study the proposed property in conjunction with test generation processes for both combinational and sequential circuits.

Circuit faults

Circuit simulation

Circuit testing

Cities and towns

Computational modeling

Electrical fault detection

Fault detection

Fault diagnosis

Sequential analysis

Sequential circuits

Details

Title: Subtitle: On avoiding undetectable faults during test generation
Creators: I Pomeranz - University of Iowa
S.M Reddy - University of Iowa
Resource Type: Conference proceeding
Publication Details: European Test Workshop 1999 (Cat. No.PR00390), pp.90-95
DOI: 10.1109/ETW.1999.804292
Publisher: IEEE
Language: English
Date published: 1999
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197268402771

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