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On determining scan flip-flops in partial-scan designs
Conference proceeding

On determining scan flip-flops in partial-scan designs

D.H Lee and S.M Reddy
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers, pp.322-325
International Conference on Computer Aided Design (ICCAD) (Santa Clara, California, USA, 11/11/1990–11/15/1990)
1990
DOI: 10.1109/ICCAD.1990.129914

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Abstract

A report is presented on procedures investigated to determine flip-flops to be scanned in partial-scan designs for sequential circuits. The main idea pursued is to derive a minimal feedback vertex set of the so-called S-graphs. Results of applying optimal and heuristic procedures on a set of benchmark circuits indicate that heuristic methods give fast and near minimal solutions.< >
Automatic testing Benchmark testing Circuit testing Cities and towns Feedback Flip-flops Hardware Sequential analysis Sequential circuits Telephony

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