Conference proceeding
On double transition faults as a delay fault model
Proceedings of the Sixth Great Lakes Symposium on VLSI, pp.282-287
Great Lakes Symposium on VLSI, 6 (Ames, Iowa, USA, 03/22/1996 - 03/23/1996)
1996
DOI: 10.1109/GLSV.1996.497634
Abstract
We define a new delay fault model, called the double transition fault model. Under this model, a fault is associated with a pair of lines and a pair of transitions on these lines. The model captures the effects of defects that increase the delays of two (or more) individual lines by an amount that causes the circuit to fail when signals are propagated through both lines. It thus provides a simplification of the path delay fault model, that does not suffer from the exponential behavior of this model. We propose a test generation procedure for double transition faults, based on reordering of a given test set for stuck-at faults. The procedure does not require enumeration of all double transition faults, and is thus applicable to circuits with large numbers of lines. We present experimental results of this procedure for several benchmark circuits.
Details
- Title: Subtitle
- On double transition faults as a delay fault model
- Creators
- I Pomeranz - University of IowaS.M Reddy - University of IowaJ.H Patel - University of Illinois at Urbana–Champaign
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings of the Sixth Great Lakes Symposium on VLSI, pp.282-287
- Conference
- Great Lakes Symposium on VLSI, 6 (Ames, Iowa, USA, 03/22/1996 - 03/23/1996)
- Publisher
- IEEE
- DOI
- 10.1109/GLSV.1996.497634
- ISSN
- 1066-1395
- Language
- English
- Date published
- 1996
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984198019402771
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