On efficient concurrent fault simulation for synchronous sequential circuits

D.H Lee; S.M Reddy

doi:10.1109/DAC.1992.227784

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Conference proceeding

On efficient concurrent fault simulation for synchronous sequential circuits

D.H Lee and S.M Reddy

[1992] Proceedings 29th ACM/IEEE Design Automation Conference, pp.327-331

ACM/IEEE Design Automation Conference, 29 (Anaheim, California, 06/08/1992 - 06/12/1992)

1992

DOI: 10.1109/DAC.1992.227784

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Abstract

The authors report on an efficient fault simulation method for synchronous sequential circuits. The method is based on concurrent fault simulation and has the simplicity of deductive fault simulation. Several new ideas to reduce computation time and memory requirements are proposed. New fault simulators were developed to simulate transition faults as well as stuck-at faults. The experimental results demonstrate that the proposed method is effective for simulating faults in large synchronous sequential circuits in the workstation environment.< >

Computer Science

Circuit faults

Circuit simulation

Circuit testing

Cities and towns

Computational modeling

Computer simulation

Propagation delay

Sequential analysis

Sequential circuits

Details

Title: Subtitle: On efficient concurrent fault simulation for synchronous sequential circuits
Creators: D.H Lee - Iowa Univ., Iowa City, IA, USA
S.M Reddy - Iowa Univ., Iowa City, IA, USA
Resource Type: Conference proceeding
Publication Details: [1992] Proceedings 29th ACM/IEEE Design Automation Conference, pp.327-331
Conference: ACM/IEEE Design Automation Conference, 29 (Anaheim, California, 06/08/1992 - 06/12/1992)
Publisher: IEEE Comput. Soc. Press
DOI: 10.1109/DAC.1992.227784
ISSN: 0738-100X
eISSN: 2374-8818
Language: English
Date published: 1992
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984198019102771

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