Conference proceeding
On generating pseudo-functional delay fault tests for scan designs
20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), pp.398-405
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 20 (Monterey, California, 10/03/2005–10/05/2005)
2005
DOI: 10.1109/DFTVS.2005.49
Abstract
In designs using DFT, such as scan, some of the faults that are untestable in the circuit without DFT become testable after DFT insertion. Additionally, scan tests may scan in illegal or unreachable states that cause nonfunctional operation of the circuit during test. This may cause higher than normal power dissipation and demands on supply current. We propose new techniques to determine illegal states of circuits that can be used during ATPG to prohibit tests using such states. The resulting tests are essentially functional or pseudofunctional.
Details
- Title: Subtitle
- On generating pseudo-functional delay fault tests for scan designs
- Creators
- Zhuo Zhang - University of IowaS.M Reddy - University of IowaI Pomeranz - Purdue University West Lafayette
- Resource Type
- Conference proceeding
- Publication Details
- 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), pp.398-405
- Conference
- IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 20 (Monterey, California, 10/03/2005–10/05/2005)
- DOI
- 10.1109/DFTVS.2005.49
- ISSN
- 1550-5774
- eISSN
- 2377-7966
- Publisher
- IEEE
- Language
- English
- Date published
- 2005
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197916502771
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