On improving a fault simulation based test generator for synchronous sequential circuits

R Guo; S.M Reddy; I Pomeranz

doi:10.1109/ATS.2001.990264

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Conference proceeding

On improving a fault simulation based test generator for synchronous sequential circuits

R Guo, S.M Reddy and I Pomeranz

Proceedings 10th Asian Test Symposium, pp.82-87

2001

DOI: 10.1109/ATS.2001.990264

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Abstract

We propose several techniques to improve a simulation based test pattern generation procedure for sequential circuits. The effectiveness of the proposed techniques is demonstrated through experimental results on a large set of benchmark circuits.

Circuit faults

Circuit simulation

Circuit testing

Compaction

Computational modeling

Fault detection

Sequential analysis

Sequential circuits

Synchronous generators

Test pattern generators

Details

Title: Subtitle: On improving a fault simulation based test generator for synchronous sequential circuits
Creators: R Guo - Intel
S.M Reddy
I Pomeranz
Resource Type: Conference proceeding
Publication Details: Proceedings 10th Asian Test Symposium, pp.82-87
Publisher: IEEE
DOI: 10.1109/ATS.2001.990264
ISSN: 1081-7735
eISSN: 2377-5386
Language: English
Date published: 2001
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197197602771

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