Conference proceeding
On interconnecting circuits with multiple scan chains for improved test data compression
17th International Conference on VLSI Design. Proceedings, pp.741-744
International Conference on VLSI Design (Mumbai, India, 01/09/2004)
2004
DOI: 10.1109/ICVD.2004.1261016
Abstract
We show that when a scan design consists of interconnected circuits, test data volume reductions can be achieved by connecting the scan chains of adjacent circuits appropriately. We formulate this problem as a problem of finding a permutation of the scan chains of one circuit with respect to another so as to minimize the number of different scan vectors required for testing both circuits. We propose a procedure for solving this problem, and present experimental results.
Details
- Title: Subtitle
- On interconnecting circuits with multiple scan chains for improved test data compression
- Creators
- Irith Pomeranz - Purdue University West LafayetteSudhakar M Reddy - University of Iowa
- Resource Type
- Conference proceeding
- Publication Details
- 17th International Conference on VLSI Design. Proceedings, pp.741-744
- Conference
- International Conference on VLSI Design (Mumbai, India, 01/09/2004)
- DOI
- 10.1109/ICVD.2004.1261016
- Publisher
- IEEE Computer Society
- Language
- English
- Date published
- 2004
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197914202771
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