Conference proceeding
On methods to improve location based logic diagnosis
19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), Vol.2006, pp.7 pp-187
2006
DOI: 10.1109/VLSID.2006.123
Abstract
The general flow of location based logic diagnosis begins with finding a set of locations which can explain one or more single location at-a time (SLAT) failing patterns [Bartenstein, 2001], then a heuristic method is used to find subsets of locations which can explain all the SLAT failing patterns are determined as the results of logic diagnosis. However, since the observed test fails may correspond to logic failures from multiple locations, the existing heuristics may find incomplete or wrong locations of the defect due to the ignorance of the correlation between the logic failure locations and the defect. In this work, we first propose several techniques to analyze the relationship of logic failure locations and collapse multiple logic failure locations into single defects, and then use a minimum set covering algorithm to find final diagnosis candidates. In this way, we can not only identify defect type but also improve diagnosis accuracy and resolution. Experimental results on both simulated defects and silicon defects are given to demonstrate effectiveness of the proposed method.
Details
- Title: Subtitle
- On methods to improve location based logic diagnosis
- Creators
- Wei Zou - University of IowaWu-Tung ChengSudhakar M Reddy - University of IowaHuaxing Tang - Mentor Graphics
- Resource Type
- Conference proceeding
- Publication Details
- 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), Vol.2006, pp.7 pp-187
- DOI
- 10.1109/VLSID.2006.123
- ISSN
- 1063-9667
- eISSN
- 2380-6923
- Publisher
- IEEE
- Language
- English
- Date published
- 2006
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197334102771
Metrics
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