Conference proceeding
On reducing peak current and power during test
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), pp.156-161
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (Tampa, Florida, 05/11/2005–05/12/2005)
2005
DOI: 10.1109/ISVLSI.2005.53
Abstract
This paper presents a progressive match filling (PMF) technique to reduce the peak current and power dissipation during the fast capture cycle in broadside delay fault testing. The proposed method fills the unspecified values (X) in the generated initialization vector such that the resulting launch vector at a minimal Hamming distance from the initialization vector. The proposed method does not require any hardware modification and can be used to obtain any test sets that require two pattern tests. Experimental results show that the proposed method reduces the peak current and power dissipation during the fast capture cycle by 40.59% on average and up to 54.17% for large ISC AS 89 circuits.
Details
- Title: Subtitle
- On reducing peak current and power during test
- Creators
- Wei Li - University of IowaSudhakar M Reddy - University of IowaIrith Pomeranz - Purdue University West Lafayette
- Resource Type
- Conference proceeding
- Publication Details
- IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), pp.156-161
- Conference
- IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (Tampa, Florida, 05/11/2005–05/12/2005)
- DOI
- 10.1109/ISVLSI.2005.53
- ISSN
- 2159-3469
- eISSN
- 2159-3477
- Publisher
- IEEE
- Language
- English
- Date published
- 2005
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197920602771
Metrics
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