Conference proceeding
On selecting testable paths in scan designs
Proceedings The Seventh IEEE European Test Workshop, Vol.2002-(January), pp.53-58
2002
DOI: 10.1109/ETW.2002.1029639
Abstract
We propose an efficient method to select a minimal set of testable paths in scan designs, such that every line in the circuit is covered by at least one of the longest testable paths that contain it (if there are any). The proposed path selection approach is based on a stepwise path expansion procedure that uses delay information and compact information about untestable paths to select longest paths while avoiding untestable paths. Techniques called delay analysis and delay-constrained path expansion are used to speedup the selection of paths to test. Compared to earlier approaches, the proposed approach is fast and it is guaranteed to find testable paths. Experimental results for ISCAS89 benchmark circuits using standard scan and broadside testing are presented to demonstrate the effectiveness of the proposed method.
Details
- Title: Subtitle
- On selecting testable paths in scan designs
- Creators
- Yun Shao - Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USASudhakar M Reddy - Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USAIrith PomeranzSeiji Kajihara
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings The Seventh IEEE European Test Workshop, Vol.2002-(January), pp.53-58
- DOI
- 10.1109/ETW.2002.1029639
- ISSN
- 1530-1877
- eISSN
- 1558-1780
- Publisher
- IEEE
- Language
- English
- Date published
- 2002
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197185702771
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