On static test compaction and test pattern ordering for scan designs

Xijiang Lin; Janusz Rajski; Irith Pomeranz; Sudhakar M Reddy

doi:10.1109/TEST.2001.966735

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Conference proceeding

On static test compaction and test pattern ordering for scan designs

Xijiang Lin, Janusz Rajski, Irith Pomeranz and Sudhakar M Reddy

Proceedings International Test Conference 2001 (Cat. No.01CH37260), pp.1088-1097

International Test Conference (ITC) (Baltimore, Maryland, USA, 11/01/2001)

2001

DOI: 10.1109/TEST.2001.966735

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Abstract

A static compaction procedure to reduce test set size for scan designs and a procedure to order test patterns in order to steepen the fault coverage curve are presented. The computational effort for both procedures is linearly proportional to the computational effort required for standard fault simulation with fault dropping. Experimental results on large industrial circuits demonstrate both the efficiency and effectiveness of the proposed procedures.

Computer Graphics

Automatic test pattern generation

Automatic testing

Circuit faults

Circuit testing

Compaction

Costs

Design engineering

Fault detection

Test pattern generators

Details

Title: Subtitle: On static test compaction and test pattern ordering for scan designs
Creators: Xijiang Lin - Mentor Graphics
Janusz Rajski - Mentor Graphics
Irith Pomeranz
Sudhakar M Reddy
Resource Type: Conference proceeding
Publication Details: Proceedings International Test Conference 2001 (Cat. No.01CH37260), pp.1088-1097
Conference: International Test Conference (ITC) (Baltimore, Maryland, USA, 11/01/2001)
DOI: 10.1109/TEST.2001.966735
ISSN: 1089-3539
eISSN: 2378-2250
Publisher: IEEE
Language: English
Date published: 2001
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197919802771

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