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On test generation for transition faults with minimized peak power dissipation
Conference proceeding

On test generation for transition faults with minimized peak power dissipation

WEI LI, Sudhakar M Reddy and Irith Pomeranz
Proceedings of the 41st annual Design Automation Conference, pp.504-509
Design automation conference (proceedings 2004)
2004
DOI: 10.1145/996566.996706

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Abstract

This paper presents a method of generating tests for transition faults using tests for stuck-at faults such that the peak power is the minimum possible using a given set of tests for stuck-at faults. The proposed method is suitable for use in testing scan designs that employ enhanced scan. The method reduces the peak power consumption in benchmark circuits by 19% on the average with essentially the same test set size and the same fault coverage compared to an earlier method.
Applied Sciences Integrated Circuits Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Testing, measurement, noise and reliability

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