On the Generation of Compact Deterministic Test Sets for BIST Ready Designs

Amit Kumar; Janusz Rajski; Sudhakar M Reddy; Thomas Rinderknecht

doi:10.1109/ATS.2013.45

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Conference proceeding

On the Generation of Compact Deterministic Test Sets for BIST Ready Designs

Amit Kumar, Janusz Rajski, Sudhakar M Reddy and Thomas Rinderknecht

2013 22nd Asian Test Symposium, pp.201-206

11/2013

DOI: 10.1109/ATS.2013.45

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Abstract

In this work we consider ATPG methods tailored to BIST ready designs to improve compression of external tests for such designs. Proposed ATPG reduces external test set sizes and test data volumes by 24% in comparison to that obtained by a state of the art commercial ATPG for BIST ready designs.

ATPG

Automatic test pattern generation

BIST Ready Design

Built-in self-test

Circuit faults

Controllability

Logic gates

Random access memory

Test Compression

Test data compression

Details

Title: Subtitle: On the Generation of Compact Deterministic Test Sets for BIST Ready Designs
Creators: Amit Kumar - University of Iowa
Janusz Rajski - Mentor Graphics
Sudhakar M Reddy - University of Iowa
Thomas Rinderknecht - Mentor Graphics
Resource Type: Conference proceeding
Publication Details: 2013 22nd Asian Test Symposium, pp.201-206
DOI: 10.1109/ATS.2013.45
ISSN: 1081-7735
eISSN: 2377-5386
Publisher: IEEE
Language: English
Date published: 11/2013
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197167802771

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