On the computation of the ranges of detected delay fault sizes

Ankan K Pramanick; Sudhakar M Reddy

doi:10.1109/ICCAD.1989.76919

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Conference proceeding

On the computation of the ranges of detected delay fault sizes

Ankan K Pramanick and Sudhakar M Reddy

1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers, pp.126-129

International Conference on Computer Aided Design (ICCAD) (Santa Clara, California, USA, 11/05/1989–11/09/1989)

1989

DOI: 10.1109/ICCAD.1989.76919

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Abstract

Existing methodologies for determining gate delay fault coverages through the computation of detected fault sizes are shown to have certain deficiencies. A method is proposed to determine all the possible ranges of detected fault sizes, thereby maximizing the fault coverage of a given test sequence. The ultimate goal of ensuring that the coverage for a particular fault extends up to the actual circuit slack is explored, and methods are given to achieve such coverages wherever possible. Results of experiments performed to evaluate the practical benefits of the proposed methods are reported.

Circuit faults

Circuit testing

Cities and towns

Clocks

Contracts

Delay

Electrical fault detection

Fault detection

Logic circuits

Performance evaluation

Details

Title: Subtitle: On the computation of the ranges of detected delay fault sizes
Creators: Ankan K Pramanick - University of Iowa
Sudhakar M Reddy - University of Iowa
Resource Type: Conference proceeding
Publication Details: 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers, pp.126-129
Conference: International Conference on Computer Aided Design (ICCAD) (Santa Clara, California, USA, 11/05/1989–11/09/1989)
DOI: 10.1109/ICCAD.1989.76919
Publisher: IEEE Comput. Soc. Press
Language: English
Date published: 1989
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197908602771

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