Conference proceeding
On the design of path delay fault testable combinational circuits
[1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium, pp.374-381
Fault-Tolerant Computing, 20 (Newcastle Upon Tyne, England, UK, 06/26/1990 - 06/28/1990)
1990
DOI: 10.1109/FTCS.1990.89391
Abstract
A theoretical framework for investigating the design for the path-delay-fault testability problem is provided. Necessary and sufficient conditions for the existence of general robust tests in a multioutput, multilevel circuit are given. The conditions for the existence of a more restricted class of robust tests are derived from those for general robust tests. A design procedure is given for the synthesis of multioutput, multilevel combinational logic circuits in which all path delay faults are robustly detectable. A powerful factorization method, that of extended factorization, was exploited for this purpose.< >
Details
- Title: Subtitle
- On the design of path delay fault testable combinational circuits
- Creators
- A.K Pramanick - University of IowaS.M Reddy - University of Iowa
- Resource Type
- Conference proceeding
- Publication Details
- [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium, pp.374-381
- Conference
- Fault-Tolerant Computing, 20 (Newcastle Upon Tyne, England, UK, 06/26/1990 - 06/28/1990)
- Publisher
- IEEE Comput. Soc. Press
- DOI
- 10.1109/FTCS.1990.89391
- ISSN
- 0731-3071
- eISSN
- 2375-124X
- Language
- English
- Date published
- 1990
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984198005002771
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