On the design of robust multiple fault testable CMOS combinational logic circuits

S Kundu; S.M Reddy; N.K Jha

doi:10.1109/ICCAD.1988.122502

Back

Conference proceeding

On the design of robust multiple fault testable CMOS combinational logic circuits

S Kundu, S.M Reddy and N.K Jha

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers, pp.240-243

International Conference on Computer Aided Design (ICCAD) (Santa Clara, California, USA, 11/07/1988–11/10/1988)

1988

DOI: 10.1109/ICCAD.1988.122502

View Online

Abstract

Tests that detect modeled faults independent of the delays in the circuit under test are called robust tests. An integrated approach to the design of combinational logic circuits in which all single stuck-open faults and path delay faults are detectable by robust tests was presented by the authors earlier. It is shown that the earlier design actually results in circuits in which all multiple stuck-at and stuck-open and multipath delay faults are robustly testable. The tests to detect such faults are presented.< >

Circuit faults

Circuit testing

CMOS logic circuits

Combinational circuits

Delay effects

Electrical fault detection

Logic testing

Robustness

Semiconductor device modeling

Timing

Details

Title: Subtitle: On the design of robust multiple fault testable CMOS combinational logic circuits
Creators: S Kundu - IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
S.M Reddy
N.K Jha
Resource Type: Conference proceeding
Publication Details: [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers, pp.240-243
Conference: International Conference on Computer Aided Design (ICCAD) (Santa Clara, California, USA, 11/07/1988–11/10/1988)
DOI: 10.1109/ICCAD.1988.122502
Publisher: IEEE Comput. Soc. Press
Language: English
Date published: 1988
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984198007802771

Metrics

17 Record Views