On the design of robust testable CMOS combinational logic circuits

S Kundu; S.M Reddy

doi:10.1109/FTCS.1988.5323

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Conference proceeding

On the design of robust testable CMOS combinational logic circuits

S Kundu and S.M Reddy

[1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers, pp.220-225

International Symposium on Fault-Tolerant Computing, 18 (Tokyo, Japan, 06/27/1988 - 06/30/1988)

1988

DOI: 10.1109/FTCS.1988.5323

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Abstract

The authors propose an integrated approach to the design of combinational logic circuits in which stuck-open faults and path delay faults are detectable by robust tests that detect modeled faults independent of the delays in the circuit under test. They demonstrate that the proposed designs and tests guarantee the design of CMOS logic circuits in which all path delay faults are locatable.< >

Circuit faults

Circuit testing

CMOS logic circuits

Combinational circuits

Delay

Electrical fault detection

Fault detection

Logic testing

Robustness

Semiconductor device modeling

Details

Title: Subtitle: On the design of robust testable CMOS combinational logic circuits
Creators: S Kundu - University of Iowa
S.M Reddy - University of Iowa
Resource Type: Conference proceeding
Publication Details: [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers, pp.220-225
Conference: International Symposium on Fault-Tolerant Computing, 18 (Tokyo, Japan, 06/27/1988 - 06/30/1988)
Publisher: IEEE Comput. Soc. Press
DOI: 10.1109/FTCS.1988.5323
ISSN: 0731-3071
eISSN: 2375-124X
Language: English
Date published: 1988
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197914502771

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