On the detection of delay faults

A.K Pramanick; S.M Reddy

doi:10.1109/TEST.1988.207872

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Conference proceeding

On the detection of delay faults

A.K Pramanick and S.M Reddy

International Test Conference 1988 Proceeding New Frontiers in Testing, pp.845-856

International Test Conference (ITC) (Washington, DC, USA, 09/12/1988 - 09/14/1988)

1988

DOI: 10.1109/TEST.1988.207872

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Abstract

The class of faults known as gate delay faults are investigated. A taxonomy of the classes of gate delay fault detecting tests is provided. Methods to derive robust and nonrobust tests to detect gate delay faults are proposed. A physically meaningful measure to assess the efficacy of test sequences is introduced, and used to report fault coverages. A nine-valued logic system was proposed and used for deriving these tests. A physically meaningful measure, in the form of the average detection size of a test sequence. An algorithm was devised and implemented to automate the process of test generation, and results of experimentation with the ATPG, as well as with a random-pattern simulator, on four ISCAS-85 circuits were reported.< >

Automatic testing

Circuit faults

Circuit testing

Delay

Fault detection

Logic testing

Robustness

Size measurement

System testing

Taxonomy

Details

Title: Subtitle: On the detection of delay faults
Creators: A.K Pramanick - University of Iowa
S.M Reddy - University of Iowa
Resource Type: Conference proceeding
Publication Details: International Test Conference 1988 Proceeding New Frontiers in Testing, pp.845-856
Conference: International Test Conference (ITC) (Washington, DC, USA, 09/12/1988 - 09/14/1988)
Publisher: IEEE Comput. Soc. Press
DOI: 10.1109/TEST.1988.207872
ISSN: 1089-3539
eISSN: 2378-2250
Language: English
Date published: 1988
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197915202771

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