Conference proceeding
On the feasibility of fault simulation using partial circuit descriptions
Proceedings of the Ninth Asian Test Symposium, pp.108-113
2000
DOI: 10.1109/ATS.2000.893611
Abstract
We investigate the feasibility of performing fault simulation for gate-level circuits using only subcircuits, without considering the complete circuit. This approach can be used to reduce the memory requirements during fault simulation of large circuits. Subcircuits for fault simulation are defined based on subsets of state variables. For every subset of state variables V, only the input cones of next state variables in V are included in the subcircuit being simulated, as well as input cones of primary outputs. We present experimental results to demonstrate the feasibility of fault simulation using subcircuits.
Details
- Title: Subtitle
- On the feasibility of fault simulation using partial circuit descriptions
- Creators
- Irith Pomeranz - Purdue University West LafayetteSudhakar M Reddy
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings of the Ninth Asian Test Symposium, pp.108-113
- DOI
- 10.1109/ATS.2000.893611
- ISSN
- 1081-7735
- eISSN
- 2377-5386
- Publisher
- IEEE
- Language
- English
- Date published
- 2000
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984196963202771
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