On the use of reset to increase the testability of interconnected finite-state machines

I Pomeranz; S.M Reddy

doi:10.1109/EDTC.1997.582416

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Conference proceeding

On the use of reset to increase the testability of interconnected finite-state machines

I Pomeranz and S.M Reddy

Proceedings European Design and Test Conference. ED & TC 97, pp.554-559

1997

DOI: 10.1109/EDTC.1997.582416

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Abstract

We propose a DFT solution for synchronous sequential circuits described as interconnections of finite-state machines, that takes into account specific requirements for justification of test sequences and propagation of fault effects occurring during test generation. We present this solution in the context of the output sequence justification problem. The proposed DFT solution is based on the use of reset. Three types of reset mechanisms are considered, having increasing overhead and increasing flexibility. The third type allows every output sequence over the output alphabet of a machine to be justified.

Circuit faults

Circuit testing

Cities and towns

Fault detection

Integrated circuit interconnections

Logic testing

Process design

Sequential analysis

Sequential circuits

Synchronous generators

Details

Title: Subtitle: On the use of reset to increase the testability of interconnected finite-state machines
Creators: I Pomeranz - Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M Reddy
Resource Type: Conference proceeding
Publication Details: Proceedings European Design and Test Conference. ED & TC 97, pp.554-559
Publisher: IEEE
DOI: 10.1109/EDTC.1997.582416
ISSN: 1066-1409
eISSN: 2377-6323
Language: English
Date published: 1997
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197221902771

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