Conference proceeding
On validating data hold times for flip-flops in sequential circuits
Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159), pp.317-325
2000
DOI: 10.1109/TEST.2000.894220
Abstract
We consider the problem of validating flip-flop data hold time requirements in sequential circuits. The data hold time violations considered are related to the presence of short paths that allow changes in next-state values to occur fast enough so as to cause latching of erroneous next-states. Three fault models are proposed that are related to the presence of short paths in the circuit. Propagation conditions for robust and non-robust tests for short paths are given. A test generation procedure is described for one of the proposed models, and experimental results are provided for benchmark circuits.
Details
- Title: Subtitle
- On validating data hold times for flip-flops in sequential circuits
- Creators
- Sudhakar M Reddy - University of IowaIrith Pomeranz - University of IowaSeiji Kajihara - Kyushu Institute of TechnologyAtsushi Murakami - Kyushu Institute of TechnologySadami Takeoka - Corporate Semiconductor Development DivisionMitsuyasu Ohta - Corporate Semiconductor Development Division
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159), pp.317-325
- DOI
- 10.1109/TEST.2000.894220
- ISSN
- 1089-3539
- eISSN
- 2378-2250
- Publisher
- IEEE
- Language
- English
- Date published
- 2000
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197209902771
Metrics
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