Conference proceeding
Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm
Proceedings - International Test Conference, pp.74-82
ITC : international test conference 2002 (Baltimore MD, 7-10 October 2002)
2002
DOI: 10.1109/TEST.2002.1041747
Abstract
This paper presents a method to consider a given SOC with pin and peak power constraints, and simultaneously (1) determine an optimal wrapper width for each core, (2) allocate SOC pins to cores and (3) schedule core tests to minimize the test completion time. For the first time the stated problem is formulated as a restricted 3 dimensional bin-packing problem and a heuristic to determine an optimal solution is proposed.
Details
- Title: Subtitle
- Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm
- Creators
- Yu Huang - Mentor GraphicsNilanjan Mukherjee - Mentor GraphicsSudhakar M Reddy - University of IowaChien-Chung Tsai - Mentor GraphicsWu-Tung Cheng - Mentor GraphicsOmer Samman - Mentor GraphicsPaul Reuter - Mentor GraphicsYahya Zaidan - Mentor Graphics
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings - International Test Conference, pp.74-82
- Conference
- ITC : international test conference 2002 (Baltimore MD, 7-10 October 2002)
- DOI
- 10.1109/TEST.2002.1041747
- ISSN
- 1089-3539
- eISSN
- 2378-2250
- Publisher
- IEEE
- Language
- English
- Date published
- 2002
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197300602771
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