PASTA: partial scan to enhance test compaction

I Pomeranz; S.M Reddy

doi:10.1109/GLSV.1999.757364

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Conference proceeding

PASTA: partial scan to enhance test compaction

I Pomeranz and S.M Reddy

Proceedings Ninth Great Lakes Symposium on VLSI, pp.4-7

Great Lakes Symposium on VLSI, 9 (Ypsilanti, Michigan, USA, 03/04/1999 - 03/06/1999)

1999

DOI: 10.1109/GLSV.1999.757364

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Abstract

We propose a procedure to select flip-flops for partial scan targeting the reduction of test length. We show that significant reductions in test length can be achieved by this procedure. In addition, experimental results show that using heuristics that target the test length does not have to increase the numbers of flip-flops that need to be scanned in order to achieve a given level of fault coverage. Consequently, it may be possible to perform partial scan selection targeting the two parameters, test length and fault coverage, without requiring more flip-flops than required for one of the parameters.

Benchmark testing

Circuit faults

Circuit testing

Cities and towns

Compaction

Electrical fault detection

Fault detection

Flip-flops

Performance evaluation

Random sequences

Details

Title: Subtitle: PASTA: partial scan to enhance test compaction
Creators: I Pomeranz - University of Iowa
S.M Reddy
Resource Type: Conference proceeding
Publication Details: Proceedings Ninth Great Lakes Symposium on VLSI, pp.4-7
Conference: Great Lakes Symposium on VLSI, 9 (Ypsilanti, Michigan, USA, 03/04/1999 - 03/06/1999)
Publisher: IEEE
DOI: 10.1109/GLSV.1999.757364
ISSN: 1066-1395
Language: English
Date published: 1999
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984198002902771

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