Conference proceeding
PERFECT case studies demonstrating order of magnitude reduction in power consumption
2016 IEEE High Performance Extreme Computing Conference (HPEC), pp.1-7
09/2016
DOI: 10.1109/HPEC.2016.7761612
Abstract
We propose three methods for reducing power consumption in high-performance FPGAs (field programmable gate arrays). We show that by using continuous hierarchy memory, lightweight checks, and lower chip voltage for near-threshold voltage computation, we can both reduce power consumption and increase reliability without a decrease in throughput. We have implemented these techniques in two different, realistic wide-area motion imagery algorithms on FPGAs. We demonstrated greatly improved performance/efficiency compared to two flight-tested platforms, getting up to a 250X reduction in power use (measured in giga operations per second per watt). This paper summarizes these two case studies.
Details
- Title: Subtitle
- PERFECT case studies demonstrating order of magnitude reduction in power consumption
- Creators
- David K Wittenberg - BAE SystemsEdin Kadric - University of PennsylvaniaAndre DeHon - University of PennsylvaniaJonathan Edwards - BAE SystemsJeffrey Smith - BAE SystemsSilviu Chiricescu - BAE Systems
- Resource Type
- Conference proceeding
- Publication Details
- 2016 IEEE High Performance Extreme Computing Conference (HPEC), pp.1-7
- Publisher
- IEEE
- DOI
- 10.1109/HPEC.2016.7761612
- Language
- English
- Date published
- 09/2016
- Academic Unit
- Cinematic Arts; English
- Record Identifier
- 9984397935702771
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