Conference proceeding
Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples
Proceedings of the 2002 Asia and South Pacific Design Automation Conference, pp.767-772
ASP-DAC '02
01/07/2002
DOI: 10.1109/ASPDAC.2002.995026
Abstract
In this work we propose a novel concept called state tuple to represent the states of lines in a circuit for the generation of two pattern tests.The proposed approach is described in detail for generating robust two pattern tests for path delay faults in standard scan designs.Using the proposed approach we also report experimental results of a test generator for robust path delay faults in standard scan designs.The results show that the test generator achieves high efficiency with reduced implementation complexity.
Details
- Title: Subtitle
- Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples
- Creators
- Yun ShaoSudhakar ReddyIrith Pomeranz
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings of the 2002 Asia and South Pacific Design Automation Conference, pp.767-772
- Publisher
- IEEE Computer Society
- Series
- ASP-DAC '02
- DOI
- 10.1109/ASPDAC.2002.995026
- Language
- English
- Date published
- 01/07/2002
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197267602771
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