Pattern sensitivity: a property to guide test generation for combinational circuits

I Pomeranz; S.M Reddy

doi:10.1109/ATS.1999.810732

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Conference proceeding

Pattern sensitivity: a property to guide test generation for combinational circuits

I Pomeranz and S.M Reddy

Proceedings Eighth Asian Test Symposium (ATS'99), pp.75-80

Asian Test Symposium, 8 (Shanghai, China, 11/18/1999)

1999

DOI: 10.1109/ATS.1999.810732

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Abstract

We propose a property of input patterns called sensitivity to guide test generation for combinational circuits. Under a sensitive pattern, a change in a single input value causes a change in an output value. Such a pattern is likely to be sensitive to the presence of a fault, and is likely to result in fault detection. We describe a test generation procedure that generates sensitive patterns based on logic simulation of the fault free circuit. The procedure achieves complete fault coverage for the circuits considered.

Circuit faults

Circuit simulation

Circuit testing

Combinational circuits

Electrical fault detection

Fault detection

Logic circuits

Logic testing

Sequential circuits

Test pattern generators

Details

Title: Subtitle: Pattern sensitivity: a property to guide test generation for combinational circuits
Creators: I Pomeranz - University of Iowa
S.M Reddy
Resource Type: Conference proceeding
Publication Details: Proceedings Eighth Asian Test Symposium (ATS'99), pp.75-80
Conference: Asian Test Symposium, 8 (Shanghai, China, 11/18/1999)
Publisher: IEEE
DOI: 10.1109/ATS.1999.810732
ISSN: 1081-7735
eISSN: 2377-5386
Language: English
Date published: 1999
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984198016702771

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