Conference proceeding
Performance aware partitioning for 3D-SOCs
2012 International SoC Design Conference (ISOCC), pp.163-166
11/2012
DOI: 10.1109/ISOCC.2012.6407065
Abstract
Through silicon vias (TSVs) have a significant impact on the area and timing performance of a 3D-SOC. Performance aware design partitioning is required to reduce delay by placing gates on critical paths close to each other on the same or adjacent dies in the 3D-SOC. Also, pre-bond test of dies in the 3D-SOC is required to insure correct functionality of the dies before bonding. Additional design for test (DFT) logic for pre-bond test also depends on the design partitions used. In this work we propose a hypergraph based multi-objective netlist partitioning scheme to improve timing performance of 3D-SOC while keeping additional DFT cost low. Accurate interconnect estimation models are incorporated during partitioning to reduce delay and interconnect length variations across dies. Results on ISCAS89 and ITC99 benchmark circuits demonstrate the improved timing performance and reduced DFT cost using the proposed approach.
Details
- Title: Subtitle
- Performance aware partitioning for 3D-SOCs
- Creators
- Amit Kumar - University of IowaSudhakar M Reddy - University of IowaBernd Becker - University of FreiburgIrith Pomeranz - Purdue University West Lafayette
- Resource Type
- Conference proceeding
- Publication Details
- 2012 International SoC Design Conference (ISOCC), pp.163-166
- DOI
- 10.1109/ISOCC.2012.6407065
- Publisher
- IEEE
- Language
- English
- Date published
- 11/2012
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197517602771
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