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Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations
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Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations

Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M Reddy, Mark Kassab, Janusz Rajski, Chen Wang, …
2020 IEEE International Test Conference (ITC), Vol.2020-, pp.1-10
11/01/2020
DOI: 10.1109/ITC44778.2020.9325219

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Abstract

Business design-for-testability (DFT) Discrete Fourier transforms Electrical engineering embedded deterministic test (EDT) Error analysis Histograms Planning scan configuration selection test compression Tools

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