Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs

Santiago Remersaro; Xijiang Lin; Zhuo Zhang; S.M Reddy; Irith Pomeranz; Janusz Rajski

doi:10.1109/TEST.2006.297694

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Conference proceeding

Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs

Santiago Remersaro, Xijiang Lin, Zhuo Zhang, S.M Reddy, Irith Pomeranz and Janusz Rajski

2006 IEEE International Test Conference, pp.1-10

10/2006

DOI: 10.1109/TEST.2006.297694

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Abstract

When the response to a test vector is captured by state elements in scan based tests, the switching activity of the circuit may be large resulting in abnormal power dissipation and supply current demand. High supply current may cause excessive supply voltage drops leading to larger gate delays which may cause good chips to fail tests. This paper presents a scalable approach called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests. Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method

Benchmark testing

Circuit faults

Circuit testing

Current supplies

Delay

Electricity supply industry

Power dissipation

Power supplies

Switching circuits

Voltage

Details

Title: Subtitle: Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs
Creators: Santiago Remersaro - University of Iowa
Xijiang Lin - Mentor Graphics (United States)
Zhuo Zhang - University of Iowa
S.M Reddy - University of Iowa
Irith Pomeranz - Purdue University West Lafayette
Janusz Rajski - Mentor Graphics (United States)
Resource Type: Conference proceeding
Publication Details: 2006 IEEE International Test Conference, pp.1-10
DOI: 10.1109/TEST.2006.297694
ISSN: 1089-3539
eISSN: 2378-2250
Publisher: IEEE
Language: English
Date published: 10/2006
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197220702771

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