Conference proceeding
Process variation-aware test for resistive bridges
IEEE transactions on computer-aided design of integrated circuits and systems, Vol.28(8), pp.1269-1274
11/03/2009
DOI: 10.1109/TCAD.2009.2021728
Abstract
This paper analyses the behaviour of resistive bridging faults under process variation and shows that process variation has a detrimental impact on test quality in the form of test escapes. To quantify this impact, a novel metric called test robustness is proposed and to mitigate test escapes, a new process variation-aware test generation method is presented. The method exploits the observation that logic faults that have high probability of occurrence and correspond to significant amounts of undetected bridge resistance have a high impact on test robustness and therefore should be targeted by test generation. Using synthesised ISCAS benchmarks with realistic bridge locations, results show that for all the benchmarks, the method achieves better results (less test escapes) than tests generated without consideration of process variation
Details
- Title: Subtitle
- Process variation-aware test for resistive bridges
- Creators
- Urban Ingelsson - University of SouthamptonBashir M Al-HashimiSaqib Khursheed - University of SouthamptonSudhakar M Reddy - University of IowaPeter Harrod - ARM (United Kingdom)
- Resource Type
- Conference proceeding
- Publication Details
- IEEE transactions on computer-aided design of integrated circuits and systems, Vol.28(8), pp.1269-1274
- DOI
- 10.1109/TCAD.2009.2021728
- ISSN
- 0278-0070
- eISSN
- 1937-4151
- Language
- English
- Date published
- 11/03/2009
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197170502771
Metrics
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