ROTCO: a reverse order test compaction technique

L.N Reddy; I Pomeranz; S.M Reddy

doi:10.1109/EUASIC.1992.228026

Back

Conference proceeding

ROTCO: a reverse order test compaction technique

L.N Reddy, I Pomeranz and S.M Reddy

Proceedings Euro ASIC '92, pp.189-194

Euro ASIC (Paris, France, 06/01/1992–06/05/1992)

1992

DOI: 10.1109/EUASIC.1992.228026

View Online

Abstract

In this paper, the authors consider the problem of reducing the test set sizes for single stuck-at faults in combinational logic circuits. They report on an alternative to the conventional reverse order fault simulation, called reverse order test compaction (ROTCO). The proposed procedure processes a test set obtained by an existing test generator, with the sim of reducing the test set size. Unlike reverse order fault simulation, the proposed procedure allows the test vectors to be changed in order to increase the flexibility in detecting faults detected by earlier vectors, thereby potentially removing tests that cannot be removed by reverse order fault simulation. Experimental results for ISCAS-85 and PLA benchmark circuits are presented to demonstrate the effectiveness of the proposed procedure.< >

Benchmark testing

Circuit faults

Circuit simulation

Circuit testing

Combinational circuits

Compaction

Electrical fault detection

Fault detection

Logic testing

Programmable logic arrays

Details

Title: Subtitle: ROTCO: a reverse order test compaction technique
Creators: L.N Reddy - University of Iowa
I Pomeranz - University of Iowa
S.M Reddy - University of Iowa
Resource Type: Conference proceeding
Publication Details: Proceedings Euro ASIC '92, pp.189-194
Conference: Euro ASIC (Paris, France, 06/01/1992–06/05/1992)
DOI: 10.1109/EUASIC.1992.228026
Publisher: IEEE Comput. Soc. Press
Language: English
Date published: 1992
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197923502771

Metrics

51 Record Views