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Reducing fault latency in concurrent on-line testing by using checking functions over internal lines
Conference proceeding

Reducing fault latency in concurrent on-line testing by using checking functions over internal lines

Irith Pomeranz and Sudhakar M Reddy
19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings, pp.183-190
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 19th (Cannes, France, 10/10/2004–10/13/2004)
2004
DOI: 10.1109/DFTVS.2004.1347839

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Abstract

Applied Sciences Electronics Exact sciences and technology Testing, measurement, noise and reliability

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