Conference proceeding
Reducing test application time for full scan circuits by the addition of transfer sequences
Proceedings of the Ninth Asian Test Symposium, pp.317-322
2000
DOI: 10.1109/ATS.2000.893643
Abstract
A test set for scan designs may consist of tests where primary input vectors are embedded between a scan-in and a scan-out operation. A static compaction procedure proposed earlier reduces the test application time of such a test set by removing the scan operations at the end of one test and at the beginning of another test, and concatenating the primary input vectors of the two tests. In this work, we investigate a method to increase the number of tests that can be combined in this way, thus further reducing the number of scan operations and the test application time. This is done by inserting one or more primary input vectors between the two tests being combined. The inserted vectors help detect faults that were originally detected due to the scan operations, allowing us to combine tests that cannot be combined otherwise. We present experimental results to demonstrate that improved levels of compaction can be achieved by this method.
Details
- Title: Subtitle
- Reducing test application time for full scan circuits by the addition of transfer sequences
- Creators
- Irith Pomeranz - Purdue University West LafayetteSudhakar M Reddy
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings of the Ninth Asian Test Symposium, pp.317-322
- DOI
- 10.1109/ATS.2000.893643
- ISSN
- 1081-7735
- eISSN
- 2377-5386
- Publisher
- IEEE
- Language
- English
- Date published
- 2000
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197106202771
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